SAE-J1850 Communication Protocol Conformity Transmission
Controller for Automotive LAN
Documents
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available. |
MSM6636.pdf
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THOMAS is a LAN monitor system for a serial communication
multiplex bus. THOMAS
Manual |
Description
The
MSM6636 is a transmission controller for automotive LAN based on data
communication protocol SAE-J1850. This LSI can realize a data bus topology bus
LAN system with a PWM bit encoding method (41.6 K bps). In addition to a
protocol control circuit, MSM6636 has an enclosed quartz oscillation circuit,
host CPU interface (clock synchronous serial / UART), a transmit/ receive
buffer, and a bus receiver circuit that decreases the burden on the host CPU.
Features
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Based on SAE-J1850 CLASS B DATA COMMUNICATION NETWORK
INTERFACE (issued August 12, 1991) |
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CSMA/CD (Carrier-sense multiple access with collision
detection) |
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Internal transmit buffer (1 frame) and receive buffer (2
frames) |
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Bit encoding: PWM (Pulse Width Modulation) |
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Transmission Speed: 41.6K bps |
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Multi-address setting with physical addressing: 1 type /
functional addressing: 15 types |
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Address filter function by multi-addressing (broadcasting
possible) |
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Automatic retransmission function by arbitration loss and non
ACK |
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3 types of in-frame response support:
1. Single-byte response from a single recipient
2.
Multi-byte response from a single recipient (with CRC code)
3. Single-byte
response from multiple recipients (ID response as ACK)
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Error detection by cyclic redundancy check (CRC) |
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Various communication error detections |
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Dual-wire bus abnormality detection by internal bus receiver
and fault tolerance function |
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Host CPU interface is LSB first / serial, 4 modes supported
1. Clock synchronous serial (no parity)
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Normal mode: 8-bit data |
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MPC Mode: 8-bit data + MPC bit (1: address / 0: data select
bit) | 2. UART (yes / no parity selectable)
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Normal mode: 1 start bit + 8-bit data + (parity) + 1 stop bit
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MPC mode: 1 start bit + 8-bit data + MPC bit + (parity) + 1
stop bit | |
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Sleep Function
Low current consumption mode by oscillation
stop (IDS Max < 50µA) SLEEP / WAKE UP control from host CPU, WAKE UP via LAN
bus |
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Available package 18pin DIP, 18 pin QFJ (PLCC) and 24pin SOP
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