In ML674K/ML675K MCUs, how do I configure the PIO pins multiplexed with SDRAM bank signals to their primary or secondary functions?
Descriptive Answer:
In ML674000, ML674001/2/3 and ML675001/2/3 MCUs, some of the PIO pins are multiplexed with SDRAM bank control signals. At any one time, these pins can be used as either PIOs or SDRAM control pins.
The role of these multiplexed functions is determined by external pin settings on the MCU. In ML674000, this role is set by input levels at the Mode[0:3] pins. In ML674001/2/3 and ML675001/2/3 MCUs, this setting is made by input level at the DRAME_N pin.
If the above noted external pins configure the DRAM block as enabled, then the particular GPIO pins multiplexed with the DRAM control signals can no longer be used and GPIOs and they only operate as DRAM signals. If these external pins disable the DRAM function, then the GPIO pins multiplexed with the DRAM signals will operate as PIO pins.
The role of these multiplexed functions is determined by external pin settings on the MCU. In ML674000, this role is set by input levels at the Mode[0:3] pins. In ML674001/2/3 and ML675001/2/3 MCUs, this setting is made by input level at the DRAME_N pin.
If the above noted external pins configure the DRAM block as enabled, then the particular GPIO pins multiplexed with the DRAM control signals can no longer be used and GPIOs and they only operate as DRAM signals. If these external pins disable the DRAM function, then the GPIO pins multiplexed with the DRAM signals will operate as PIO pins.
